----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:31:03 10/09/2013 
-- Design Name: 
-- Module Name:    Dem10 - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
  
entity Dem10 is
    Port ( CLK : in  STD_LOGIC;
			  RESET : in  STD_LOGIC;
			  DIR : in  STD_LOGIC;
			  Q : out STD_LOGIC_VECTOR(3 DOWNTO 0);
			  FLAG : OUT STD_LOGIC);
end Dem10;

architecture Behavioral of Dem10 is
	type FSM_States is (NUM0,NUM1, NUM2, NUM3, NUM4, NUM5, NUM6, NUM7, NUM8, NUM9);
	signal CurrentState, NextState: FSM_States;
begin
	OutputLogic: process(CurrentState,DIR) is
	begin
		case CurrentState is
			when NUM0 =>
				Q <= "0000";
			when NUM1 =>
				Q <= "0001";
			when NUM2 =>
				Q <= "0010";
			when NUM3 =>
				Q <= "0011";
			when NUM4 =>
				Q <= "0100";
			when NUM5 =>
				Q <= "0101";
			when NUM6 =>
				Q <= "0110";
			when NUM7 =>
				Q <= "0111";
			when NUM8 =>
				Q <= "1000";
			when NUM9 =>
				Q <= "1001";
		end case;
	end process;
	
	NextStateLogic:
	process(CurrentState, DIR) is
	begin
		case CurrentState is
			when NUM0 =>
				if(DIR = '0') then
					NextState <= NUM1;
				else
					NextState <= NUM9;
				end if;
			when NUM1 =>
				if(DIR = '0') then
					NextState <= NUM2;
				else
					NextState <= NUM0;
				end if;
			when NUM2 =>
				if(DIR = '0') then
					NextState <= NUM3;
				else
					NextState <= NUM1;
				end if;
			when NUM3 =>
				if(DIR = '0') then
					NextState <= NUM4;
				else
					NextState <= NUM2;
				end if;
			when NUM4 =>
				if(DIR = '0') then
					NextState <= NUM5;
				else
					NextState <= NUM3;
				end if;
			when NUM5 =>
				if(DIR = '0') then
					NextState <= NUM6;
				else
					NextState <= NUM4;
				end if;
			when NUM6 =>
				if(DIR = '0') then
					NextState <= NUM7;
				else
					NextState <= NUM5;
				end if;
			when NUM7 =>
				if(DIR = '0') then
					NextState <= NUM8;
				else
					NextState <= NUM6;
				end if;
			when NUM8 =>
				if(DIR = '0') then
					NextState <= NUM9;
				else
					NextState <= NUM7;
				end if;
			when NUM9 =>
				if(DIR = '0') then
					NextState <= NUM0;
				else
					NextState <= NUM8;
				end if;
		end case;
	end process;
	
	StateRegister:
	process(NextState, CLK, RESET) is
	begin
		if(RESET = '1') then
			CurrentState <= NUM0;
			FLAG <= '0';
		elsif (Clk'event and Clk = '1') then
			CurrentState <= NextState;
			if(DIR = '0' and CurrentState = NUM9) then
				FLAG <= '1';
			elsif(DIR = '1' and CurrentState = NUM0) then
				FLAG <= '1';
			else
				FLAG <= '0';
			end if;
		end if;
	end process;
end Behavioral;

